New PDF release: Design Automation for Timing-Driven Layout Synthesis

By Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

ISBN-10: 1461363934

ISBN-13: 9781461363934

ISBN-10: 1461531780

ISBN-13: 9781461531784

Moore's legislations [Noy77], which estimated that the variety of units in­ tegrated on a chip will be doubled each years, used to be exact for a couple of years. just recently has the extent of integration be­ gun to decelerate a bit a result of actual limits of integration know-how. Advances in silicon know-how have allowed Ie layout­ ers to combine various million transistors on a chip; even an entire procedure of reasonable complexity can now be applied on a unmarried chip. to maintain speed with the expanding complexity in very huge scale built-in (VLSI) circuits, the productiveness of chip designers must elevate on the similar cost because the point of integration. with no such a rise in productiveness, the layout of complicated structures will not be achieveable inside a cheap time frame. The quickly expanding complexity of VLSI circuits has made de- 1 2 advent signal automation an absolute necessity, because the required elevate in productiveness can basically be comprehensive with using refined layout instruments. Such instruments additionally permit designers to accomplish trade-off analyses of alternative common sense implementations and to make well-informed layout decisions.

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3) One of the nonground nodes of the tree is assumed to be the input, and one or more nodes the outputs. As a consequence of (1) and (2), there is a unique path through the resistive path of the network from any nonground node to the input node. 3: An RC tree. 3. The input node of the network is the one marked "IN". Note that this tree satisfies the three properties listed above. An RC mesh has the same three primitive elements as an RC tree. The difference lies in the recursive definition: any two RC meshes with a common ground node and one or more nonground nodes from each tree connected together form a new RC mesh.

Let Cis denote the standard capacitance in the ith primitive. 1 pF for i = 4,5. A primitive is a standard primitive if RD = RDS, RL = RLS, and C1 = CIS in primitive 1. Rp = Rps, C2 = C 2S(C3S) in primitive 2 (primitive 3). Rp = Rps, C2 = C4S (C 5S ) in primitive 4 (primitive 5). 3. MACROMODELING 39 In primitives 4 and 5, two dimensionless quantities, (3 = RD/ Rp, and, = Cl/C 2 , are defined, and are used to completely specify the standard primitive. (3 and I are allowed to vary over the ranges [(3min, (3ma:z:] and [{min, ,ma:z:], respectively.

The current flowing through the nFET is essentially equal to the discharge current iL. 5VDD over the time period t2. 40) The following cubic equation is obtained. 41) The time t2 can be solved using a cubic root formula [Bey78]. Again, depending on whether tt + t'J is greater than t r , we can have the following two cases. 1 : tl + tl < tr The output voltage drops to half of VDD while the input signal is still in its positive-going stage. The delay time is the summation of both stages or td = tl +t2.

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Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

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